1. Field of the Invention
The specification, drawings, and claims of this application (hereinafter referred to as “this specification and the like”) relate to, for example, a semiconductor device, an electronic component, an electronic device, operating methods thereof, and manufacturing methods thereof. Examples of a technical field of one embodiment of the present invention include a semiconductor device, a memory device, a processing unit, a switch circuit (e.g., a power switch and a wiring switch), a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, an input device, an imaging device, a driving method thereof, and a manufacturing method thereof.
2. Description of the Related Art
As memory cells used in random access memories (RAM), 1T1C (one transistor-one capacitor)-type memory cells and 2T-type or 3T-type memory cells are known. These memory cells store data by charging and discharging retention nodes with write transistors.
It has been proposed that a transistor whose channel formation region is formed using an oxide semiconductor (hereinafter also referred to as an oxide semiconductor transistor or an OS transistor) is employed as a write transistor in these memory cells. For example, Patent Document 1 discloses a memory cell that can retain data even in the situation in which electric power is not supplied, by including the OS transistor as a writing transistor. A memory device including an OS transistor can be used as a nonvolatile memory.
In a memory device including the OS transistor described in Patent Document 1, each memory cell does not have an amplification function, which is different from a static RAM (SRAM) cell. Therefore, in data writing, writing needs to be performed on all of memory cells connected to a word line to be selected. That is, writing cannot be performed in units smaller than the line size. For example, in the case where a word is 32 bits and the line size is 128 bits (16 bytes), write access in byte (8-bit) units, a half-word (2-byte) units, and word (4-byte) units cannot be performed.
A hierarchical word line structure (also called divided word line structure) including a global word line and a local word line is proposed (e.g., Patent Document 2) to solve the above problem. This structure reduces the number of memory cells connected to a local word line and allows writing in byte units, half-word units, and word units, for example. However, to achieve the hierarchical structure including a global word line and a local word line, a logic circuit such as an AND circuit needs to be inserted to a connection portion of the global word line and the local word line. For byte writing, for example, the local word line needs to be provided for every eight memory cells. In this case, a word line divider (e.g., an AND circuit) is inserted in every eight columns, which causes a significantly large increase in area due to the insertion of the word line divider. Also in the cases where writing is performed in half-word (16-bit) units and word (32-bit) units, a large increase in area due to the insertion of the AND circuit is caused.
In order to solve such problems, Patent Document 3 proposes the insertion of an OS transistor in a connection portion of a word line and a sub word line to reduce the size of a word line divider.